[Main menu]

We need a title !!!

Interrupt Descriptor Table


The Interrupt Descriptor Table (IDT) is used by the Intel architechture for handling interrupts.

Table Description

The different fields in the IDT table have the following layout. This is not the layout of the actual IDT as used be the system, but only a logical layout of how the system uses the IDT.

The IDT Table

This table shows how the Interrupt Descriptor Table is going to be used by the Maverick Operating System.

Interrupt Descriptor Table
INT Vector #Interrupt TypeDescriptionGroup
00h Divided by 0 Intel reserved
01h Exception Debugger exception
02h NMI Interrupt
03h Exception Breakpoint
04h INTO-detected Overflow
05h Exception BOUND Range Exceeded
06h Invalid Opcode
07h Device Not Available
08h Double Fault
09h Not used on Pentium
0Ah Invalid Task State Segment
0Bh Exception Segment Not Present
0Ch Exception Stack Exception
0Dh General Protection
0Eh Page Fault
0Fh Intel Reserved
10h Floating Point Error
11h Alignment Check
12h Exception Machine Check Execption
13h Intel Reserved
... ...
1Fh ...
20h Not Yet Defined OS Reserved
... ...
4Fh ...
50h ISR Systemtimer IRQ Service Routines
51h ISR Keyboard
52h ISR PIC-2
53h ISR IRQ routine assigned by HIL Manager
... ... ...
5Fh ISR ...
60h Not Yet Defined OS Reserved
... ...
7Fh ...
80h Software Get Function ID Message Passing Interface
81h Software Send Message
82h Software Get Message
83h Not Yet Defined OS Reserved
... ...
FFh ...

Use DPL of 0, for all interrupts 0-1Fh. The processor exceptions will ignore the DPL, but code with CPL 1-3 will generate protection fault (as it should because they may not call these interrupts).